1. Field of the Invention
This invention relates to digital video tape recorder apparatus, and is particularly concerned with the regeneration of a clock pulse signal from a stream of data being reproduced by a digital video tape recorder (VTR) from a magnetic tape.
2. Description of the Prior Art
Clock pulse signal recovery is a particular problem where data is being derived from a noisy source, such as off tape by a digital VTR. Because of the high sampling rate required to digitize a television signal, there is generally no spare capacity available when recording on a digital VTR to record clock information, and regeneration from the reproduced stream of data is therefore necessary.
Initially a tuned circuit was used for clock regeneration or recovery, the tuned circuit resonating at the clock frequency. However, this technique is only satisfactory in cases where the code used for recording has a strong clock component, and there is a large and reasonably continuous amount of clock information in the reproduced data; because if there is a significant gap in the reproduced clock information, the tuned circuit will cease to resonate. In the case of digital television signals coming off tape there are substantial gaps in which there is no clock information at all. It has therefore been proposed to use a phase-locked loop (PLL) circuit arrangement.
A PLL circuit arrangement can be designed with some of the characteristics of a tuned circuit, in particular a narrow bandwidth and a strong pick-up of the required frequency, but with the additional advantage that in the temporary absence of incoming clock information the PLL circuit can effectively act as a sample-and-hold circuit, with the output continuing at a value determined by the last-received clock information.
In the case of a stream of data derived from the tape of a single-speed digital VTR, each field of the data contains a substantial amount of useful information, but for some 10% of each rotation of the magnetic head assembly of the VTR no useful data is derived because the magnetic head is not engaging the tape. The envelope of the derived data, which envelope has a frequency of 50 Hz, therefore includes some 90% with useful clock information, although even in this part of the envelope there may be significant gaps in the clock information due to drop-out on reproduction or to the characteristics of the actual picture content represented by the data. The PLL circuit has the ability to bridge any such gap and to pick-up and correct quickly to any change in the clock frequency following such a gap.
Referring to FIG. 1 of the accompanying drawings, this shows a previously-proposed PLL circuit arrangement for clock regeneration. Data derived from the tape of a single-speed digital VTR is supplied by way of an input terminal 1 to one input of an exclusive-OR gate 2, the incoming data from the input terminal 1 also being supplied by way of a delay device 3 which introduces a delay of t, to a second input of the exclusive-OR gate 2. The output of the exclusive-OR gate 2 is connected to respective inputs of AND gates 4 and 5, the outputs of which, inverted in the case of the AND gate 5, are connected to respective current pump circuits 6 and 7, the outputs of which are connected in common to a loop filter 8. The output of the loop filter 8 is a voltage which is supplied to a voltage controlled oscillator (VCO) 9 which produces a clock signal CLK and also an inverted clock signal CLK, the clock frequency being controlled in dependence on the voltage supplied by the loop filter 8. The clock signal CLK and the inverted clock signal CLK are respectively supplied to second input terminals of the AND gates 4 and 5.
The operation is as follows. The exclusive-OR gate 2 and the delay device 3 together have the effect of differentiating the incoming data, and at the output of the exclusive-OR gate 2 there are produced pulses of duration t, one such pulse being produced for each edge, both positive and negative, of the incoming data. It is necessary that t be less than, or at most equal to, half the clock period of the incoming data.
If the differentiated pulses supplied by the exclusive-OR gate 2 to the AND gates 4 and 5 move in phase relation to the clock pulse signal CLK (or CLK), one of the AND gates 4 or 5 will produce a wider output pulse than the other. The loop will settle, that is to say become correctly locked, when the edges of the clock pulse signal CLK (or CLK) are centred in the data pulses supplied by the exclusive-OR gate 2. This part of the circuit arrangement therefore forms a phase detector, and this particular form of phase detector is sometimes called a charge pump phase detector.
The loop filter 8 largely determines the characteristics of the phase-locked loop. In a particular example of the PLL circuit arrangement of FIG. 1, the operating frequency is 50 MHz, the hold range is .+-.500 KHz, the capture range is 1 MHz, the loop bandwidth is 200 KHz and the accuracy of data regeneration is within .+-.1 nanosecond.
There is, however, a problem, and this is that if the loop filter bandwidth is too small, the PLL circuit can lock out. This occurs when the voltage supplied to the VCO 9 is at one end of the range when it should be at the other. In this case the loop filter 8 integrates the frequency difference and no error is apparent. To overcome this problem the bandwidth of the loop filter 8 must be wide, but the wider this bandwidth is made the less effective the arrangement is in reducing the noise modulation. In the case of data off the tape of a digital VTR, therefore, which data is subject to severe noise modulation, it is rather difficult to find a satisfactory compromise design for the loop filter 8 which will sufficiently reduce the noise modulation without, at the same time, causing lock out.
This difficulty is compounded in the case of a digital VTR the speed of which is to be varied on reproduction in order to achieve special effects such as fast-motion, slow-motion and stop-motion. Where the normal replay speed results in a data rate of 50 Megabits per second, the special effects may cause the data rate to change to somewhere in the range of 35 to 65 Megabits per second.
In an attempt to deal with these problems we have previously proposed in our UK patent application No. 8029485 (Ser. No. 2 084 415) a dual phase-locked loop arrangement in which selection of a special effect mode causes a pre-set control voltage to be applied to respective VCOs in the two phase-locked loops. However, this arrangement is difficult to design and does not operate wholly satisfactorily in practice, as the arrangement can still lock out.